A Floating-Gate-Based Field-Programmable Array of Analog and Digital Devices

A hybrid, mixed-signal, reconfigurable system, based on the combination of a field-programmable analog array (FPAA) and FPGA is presented. The chip is a fine-grained interleaving of interchangeable analog and digital tiles, wherein a tile comprises either analog or digital computational elements and interconnect. The chip comprises the array core, high-speed I/O, and floating-gate programming infrastructure that communicates over a standard SPI bus. The FPAADD consists of 27 x 8 array of 108 digital and 108 analog tiles and peripheral circuitry on 5 x 5 mm die fabricated in a 0.35-μm CMOS process. The chip’s 132,000 FG switch elements are tunable from less than 10 kΩ to greater than 10 GΩ effective resistance at programming rates exceeding 1 μs for 1-b accuracy and 50 ms for 9-b accuracy. The computational analog blocks contain a variety of subcircuits: programmable offset wide-linear-range OTAs to nMOS and pMOS transistors, and interconnect. The digital tiles contain combinational logic blocks of homogenous clusterings of lookup tables and flip-flops and interconnect. The routing scheme was designed to reduce local interconnect parasitic capacitance and utilize a lightweight Manhattan style global interconnect. Measured results of low level computational elements and routing infrastructure and preliminary system results are presented.